--------------------------------------------------------------------------------
-- Company: 			StrathSat-R	
-- Engineer:			Thomas Parry
--
-- Create Date:   	22:34:34 08/07/2012
-- Design Name:   
-- Module Name:   	StrathSat-R/svn/trunk/VHDL/data_storage/sd_host/data_tx_tb.vhd
-- Project Name:  	sd_host
-- Target Device:  	Spartan 6
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: data_tx
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY data_tx_tb IS
END data_tx_tb;
 
ARCHITECTURE behavior OF data_tx_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    component data_tx
	 generic
		(
			DATA_LENGTH		:	integer;
			INPUT_WIDTH		:	integer;
			CRC_LENGTH		:	integer
		);
    port(
         Clk 			: in  	std_logic;
         Strobe 		: in  	std_logic;
         Data 			: in  	std_logic_vector(7 downto 0);
         Output 		: out  	std_logic;
         Done 			: out  	std_logic;
			Data_Req		: out		std_logic
        );
    end component;
    
	 constant DATA_LENGTH 	: 	integer := 4096;
	 constant INPUT_WIDTH	:	integer := 8;

   --Inputs
   signal Clk 			: std_logic := '0';
   signal Strobe 		: std_logic := '0';
   signal Data 		: std_logic_vector(INPUT_WIDTH-1 downto 0) := (others => '0');

 	--Outputs
   signal Output 		: std_logic;
   signal Done 		: std_logic;
	signal Data_Req	: std_logic;

   -- Clock period definitions
   constant Clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: data_tx 
			generic map
			(
				DATA_LENGTH => data_length,
				INPUT_WIDTH	=>	8,
				CRC_LENGTH  => 16
			)
			PORT MAP (
          Clk => Clk,
          Strobe => Strobe,
          Data => Data,
          Output => Output,
          Done => Done,
			 Data_Req => Data_Req
        );

   -- Clock process definitions
   Clk_process :process
   begin
		Clk <= '0';
		wait for Clk_period/2;
		Clk <= '1';
		wait for Clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for Clk_period*10;

      -- insert stimulus here
		Data		<= X"30";
		Strobe	<= '1';
		
		wait for Clk_period;
		
		Strobe	<= '0';

      wait;
   end process;

END;
